1. Field of the Invention
This invention concerns an arrangement for controlling certain internal operations in a data processing system. It pertains, more particularly, to apparatus for controlling operations forced by specific conditions in the control unit of a data processing system.
2. Description of the Prior Art
It is often necessary with particular states during the internal program flow of an electronic data processing system to delay the execution of a current instruction to permit the insertion of wait cycles. It may also be necessary to interrupt instruction execution to insert a particular number of wait cycles, for example, for channel access to common storage of the data processing system, for reloading a data or an instruction buffer, or for like control situations. In all these cases, it is necessary for the control unit to ignore the instruction awaiting execution and to execute another forced operation instead.
Prior art control units found in known data processing systems, such as the IBM System 370, Model 115, for example, contain such essential elements as control storage and data flow control gates. In addition, they include an instruction register, a clock pulse generator, an operation decoder and a priority logic circuit. The priority logic circuit arranges, in accordance with a predetermined weighting, the waiting internal or external machine conditions which would dictate an interrupt and in response thereto generates the bits necessary for an operation forced by said conditions.
The priority circuit is understandably complex. It includes many logic gates that perform combinational tasks, circuits for inhibiting and enabling control signal flow and circuits for generating certain of the control signals themselves. Unfortunately, such an overall circuit structure is disadvantageous with regard to its manufacturing costs, the number of components required and its error rate.